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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20812-3E
FLASH MEMORY
CMOS
4M (512K x 8/256K x 16)
MBM29F400TA/MBM29F400BA
s DISTINCTIVE CHARACTERISTICS
* Single 5.0 V read, write, and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard word-wide pinouts 48-pin TSOP (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin SOP (Package suffix: PF) * Minimum 100,000 write/erase cycles * High performance 70 ns maximum access time * Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Low power consumption 20 mA typical active read current for Byte Mode 28 mA typical active read current for Word Mode 30 mA typical write/erase current 25 A typical standby current * Low VCC write inhibit 3.2 V * Sector protection Hardware method disables any combination of sectors from write or erase operations * Temporary sector unprotection Hardware method enable temporarily any combination of sectors from write or erase operations. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29F400TA/MBM29F400BA
s PACKAGE
Marking Side
Marking Side
Marking Side
(FPT-48P-M19) 48-pin TSOP
(FPT-48P-M20)
(FPT-44P-M16) 44-pin SOP
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MBM29F400TA/MBM29F400BA
s GENERAL DESCRIPTION
The MBM29F400TA/BA is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The MBM29F400TA/BA is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The MBM29F400TA/BA is erased when shipped from the factory. The standard MBM29F400TA/BA offers access times between 70 ns and 120 ns, allowing operation of highspeed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The MBM29F400TA/BA is pin and command set compatible with JEDEC standard 4M-bit E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices. The MBM29F400TA/BA is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than one second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire chip or any individual sector is typically erased and verified in 1.5 seconds. (If already completely preprogrammed.) This device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY pin. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29F400TA/BA memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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MBM29F400TA/MBM29F400BA
s FLEXIBLE SECTOR-ERASE ARCHITECTURE
* One 16K byte, two 8K bytes, one 32K byte and seven 64K bytes. * Individual-sector, multiple-sector, or bulk-erase capability. * Individual or multiple-sector protection is user definable.
7FFFFH 16K byte 7BFFFH 8K byte 79FFFH 8K byte 77FFFH 32K byte 6FFFFH 64K byte 5FFFFH 64K byte 4FFFFH 64K byte 3FFFFH 64K byte 2FFFFH 64K byte 1FFFFH 64K byte 0FFFFH 64K byte 00000H MBM29F400TA Sector Architecture MBM29F400BA Sector Architecture 16K byte 8K byte 8K byte 32K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte 64K byte
7FFFFH 6FFFFH 5FFFFH 4FFFFH 3FFFFH 2FFFFH 1FFFFH 0FFFFH 07FFFH 05FFFH 03FFFH 00000H
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MBM29F400TA/MBM29F400BA
s PRODUCT SELECTOR GUIDE
Part No. Ordering Part No. Max. Access Time (ns) CE Access (ns) OE Access (ns) VCC = 5.0 V5% VCC = 5.0V10% -70 -- 70 70 30 MBM29F400TA/MBM29F400BA -- -90 90 90 35 -- -12 120 120 50
s BLOCK DIAGRAM
RY/BY Buffer VCC VSS
DQ0 to DQ15 RY/BY
Erase Voltage Generator
Input/Output Buffers
WE BYTE RESET State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch
STB
Y-Decoder
Y-Gating
VCC Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0 to A17 A-1
5
MBM29F400TA/MBM29F400BA
s CONNECTION DIAGRAMS
TSOP A15 A14 A13 A12 A11 A10 A9 A8 N.C. N.C. WE RESET N.C. N.C. RY/BY N.C. A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SOP (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 N.C. RY/BY A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
(Marking Side)
MBM29F400TA/MBM29F400BA Standard Pinout
FPT-48P-M19 A1 A2 A3 A4 A5 A6 A7 A17 N.C. RY/BY N.C. N.C. RESET WE N.C. N.C. A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
(Marking Side)
MBM29F400TA/MBM29F400BA Reverse Pinout
FPT-44P-M16
FPT-48P-M20
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MBM29F400TA/MBM29F400BA
s LOGIC SYMBOL
Table 1 Pin
A-1 18 A0 to A17 DQ0 to DQ15 16 or 8
MBM29F400TA/BA Pin Configuration Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready-Busy Output Hardware Reset Pin/Sector Protection Unlock Selects 8-bit or 16-bit mode No Internal Connection Device Ground Device Power Supply (5.0 V10% or 5%)
A-1, A0 to A17 DQ0 to DQ15 CE OE
CE OE WE RESET BYTE RY/BY
WE RY/BY RESET BYTE N.C. VSS VCC
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MBM29F400TA/MBM29F400BA
s ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29F400
TA
-70
PFTN
PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PF = 44-Pin Small Outline Package SPEED OPTION See Product Selector Guide BOOT CODE SECTOR ARCHITECTURE TA = Top sector BA = Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29F400 4Mega-bit (512K x 8-Bit or 256K x 16-Bit) CMOS Flash Memory 5.0 V-only Read, Write, and Erase
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MBM29F400TA/MBM29F400BA
Table 2 Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (2) Standby Output Disable Write Enable Sector Protection (3) Verify Sector Protection (3) Temporary Sector Unprotection Reset (Hardware)/Standby MBM29F400TA/BA User Bus Operations (BYTE = VIH) CE L L L H L L L L X X OE L L L X H H VID L X X WE H H H X H L L H X X A0 L H A0 X X A0 X L X X A1 L L A1 X X A1 X H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ0 to DQ15 Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z RESET H H H H H H H H VID L
Table 3 Operation
MBM29F400TA/BA User Bus Operations (BYTE = VIL) CE L L L H L L L L X X OE L L L X H H VID L X X WE H H H X H L L H X X DQ15/A-1 L L A-1 X X A-1 X L X X A0 L H A0 X X A0 X L X X A1 L L A1 X X A1 X H X X A6 L L A6 X X A6 L L X X A9 VID VID A9 X X A9 VID VID X X DQ0 to DQ7 Code Code DOUT HIGH-Z HIGH-Z DIN X Code X HIGH-Z RESET H H H H H H H H VID L
Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (2) Standby Output Disable Write Enable Sector Protection (3) Verify Sector Protection (3) Temporary Sector Unprotection Reset (Hardware)/Standby
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 7. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Refer to the section on Sector Protection.
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MBM29F400TA/MBM29F400BA
Read Mode
The MBM29F400TA/BA has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tCE time.)
Standby Mode
There are two ways to implement the standby mode on the MBM29F400TA/BA device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC0.3 V. Under this condition the current consumed is less than 100 A. A TTL standby mode is achieved with CE and RESET pins held at VIH. Under this condition the current is reduced to less than 1 mA. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VCC0.3 V (CE = H or L). Under this condition the current consumed is less than 100 A. A TTL standby mode is achieved with RESET pin held at VIL (CE= H or L). Under this condition the current is reduced to less than 1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
Output Disable
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A0, A1 and A6. The manufacturer and device codes may also be read via the command register, for instances when the MBM29F400TA/BA is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 7. (Refer to Autoselect Command section.) A0 = VIL represents the manufacturer's code (Fujitsu = 04H) and A0 = VIH represents the device identifier code (MBM29F400TA = 23H and MBM29F400BA = ABH for x8 mode; MBM29F400TA = 2223H and MBM29F400BA = 22ABH for x16 mode). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 4.1 and 4.2.)
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MBM29F400TA/MBM29F400BA
Table 4.1 MBM29F400TA/BA Sector Protection Verify Autoselect Codes Type Manufacturer's Code Byte MBM29F400A Device Code MBM29F400TA Word Byte MBM29F400BA Word Sector Protection *1: A-1: Byte mode *2: Outputs 01H at protected sector addresses Table 4.2 Expanded Autoselect Code Table Type Manufacturer's Code Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04H A-1/0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 Sector Addresses VIL VIH VIL X VIL VIL VIH X VIL 22ABH 01H*2 X VIL VIL VIH X VIL 2223H ABH A12 to A17 X A6 VIL A1 VIL A0 VIL A-1*1 VIL VIL Code (HEX) 04H 23H
MBM29F400TA (B) 23H A-1 MBM29F400A (W) 2223H 0 Device MBM29F400BA (B) ABH A-1 Code (W) 22ABH 0 Sector Protection (B): Byte mode (W): Word mode 01H A-1/0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 0 1 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 0 1 0 0 0 0 0 0 0 0
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F400TA/BA feature hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming equipment at the user's site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V) and CE = VIL and A6 = VIL. The sector addresses (A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. Tables 5 and 6 define the sector address for each of the eleven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
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MBM29F400TA/MBM29F400BA
rising edge of the same. Sector addresses must be held constant during the WE pulse. Refer to figures 14 and 20 for sector protection algorithm and waveforms. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A17, A16, A15, A14, A13 and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6 are DON'T CARE. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses (A17, A16, A15, A14, A13 and A12) are the sector address will produce a logical "1" at DQ0 for a protected sector. See Table 4.1 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29F400TA/BA devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again.
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MBM29F400TA/MBM29F400BA
Table 5 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A17 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 1 1 1 Sector Address Tables (MBM29F400TA) A15 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X 0 1 1 1 A13 X X X X X X X X 0 0 1 A12 X X X X X X X X 0 1 X Address Range 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 77FFFH 78000H to 79FFFH 7A000H to 7BFFFH 7C000H to 7FFFFH
Table 6 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 A17 0 0 0 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1
Sector Address Tables (MBM29F400BA) A15 0 0 0 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X A13 0 1 1 X X X X X X X X A12 X 0 1 X X X X X X X X Address Range 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH
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MBM29F400TA/MBM29F400BA
Table 7 Command Sequence Word Byte Bus Write Cycles Req'd 1 First Bus Write Cycle Addr. MBM29F400TA/BA Command Definitions
Fifth Bus Sixth Bus Second Bus Third Bus Fourth Bus Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data -- -- -- -- -- -- -- -- -- --
Read/Reset* Read/Reset*
XXXXH F0H
Word 3 Byte Word Autoselect 3 Byte Word Program 4 Byte Word Chip Erase 6 Byte Word Sector 6 Erase Byte Sector Erase Suspend Sector Erase Resume
5555H 2AAAH 5555H AAH 55H F0H RA RD -- -- -- -- AAAAH 5555H AAAAH 5555H 2AAAH 5555H AAH 55H 90H -- -- -- -- -- -- AAAAH 5555H AAAAH 5555H 2AAAH 5555H AAH 55H A0H PA PD -- -- -- -- AAAAH 5555H AAAAH 5555H 2AAAH 5555H 5555H 2AAAH 5555H AAH 55H 80H AAH 55H 10H AAAAH 5555H AAAAH AAAAH 5555H AAAAH 5555H 2AAAH 5555H 5555H 2AAAH AAH 55H 80H AAH 55H SA 30H AAAAH 5555H AAAAH AAAAH 5555H Erase can be suspended during sector erase with Addr (H or L). Data (B0H) Erase can be resumed after suspend with Addr (H or L). Data (30H)
Notes: 1. Address bits A15 to A17 = X = H or L for all address commands except or Program Address (PA) and Sector Address (SA). 2. Bus operations are defined in Tables 2 and 3. 3. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of WE. 5. The system should generate the following address patterns: Word Mode: 5555H or 2AAAH to addresses A0 to A14 Byte Mode: AAAAH or 5555H to addresses A-1 to A14 * : Either of the two reset commands will reset the device.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/ Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
Read/Reset Command
The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. 14
MBM29F400TA/MBM29F400BA
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for x16 (XX02H for x8) returns the device code (MBM29F400TA = 23H and MBM29F400BA = ABH for x8 mode; MBM29F400TA = 2223H and MBM29F400BA = 22ABH for x16 mode). (See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector. To terminate the operation, it is necessary to write the read/reset command sequence into the register and also to write the auto select command during the operation, execute it after writing read/reset command sequence.
Byte/Word Programming
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded ProgramTM Algorithm command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit (See Write Operation Status section.) at which time the device returns to the read mode and addresses are no longer latched. Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If operating hardware reset durning the programming, it is impossible the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. Figure 15 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
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MBM29F400TA/MBM29F400BA
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded EraseTM Algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to read the mode. Figure 16 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data=30H) is latched on the rising edge of WE . A time-out of 50 s from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 s from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 s time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in that sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See Write Operation Status section.) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Figure 16 illustrates the Embedded Erase Algorithm using typical command strings and bus operations.
Erase Suspend
Erase Suspend command allows the user to interrupt the chip and then perform data reads (not program) from a non-busy sector during a Sector Erase operation. (Which may take up to several seconds.) This command is applicable ONLY during the Sector Erase operation and will be ignored if written during the chip Erase or Programming operation. The Erase Suspend command (B0H) which is allowed only during the Sector Erase Operation includes the sector erase time-out period after the Sector Erase commands (30H). Writing this command during the time-out will result in immediate termination of the time-out period. Any subsequent writes of the Sector Erase command will be taken as the Erase Resume command. Note that any other commands during the time out will reset the device to read mode. The addresses are DON'T CARES when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during a Sector Erase operation, the chip will take between 0.1 s to 15 s to suspend the erase operation and go into erase suspended read mode (pseudo-read mode), during 16
MBM29F400TA/MBM29F400BA
which the user can read from a sector that is NOT being erased. A read from a sector being erased may result in invalid data. The user must monitor the toggle bit (DQ6) to determine if the chip has entered the pseudo-read mode, at which time the toggle bit stops toggling. An address of a sector NOT being erased must be used to read the toggle bit, otherwise the user may encounter intermittent problems. Note that the user must keep track of what state the chip is in since there is no external indication of whether the chip is in pseudo-read mode or actual read mode. After the user writes the Erase Suspend command, the user must wait until the toggle bit stops toggling before data reads from the device can be performed. Any further writes of the Erase Suspend command at this time will be ignored. Every time an Erase Suspend command followed by an Erase Resume command is written, the internal (pulse) counters are reset. These counters are used to count the number of high voltage pulses the memory cell requires to program or erase. If the count exceeds a certain limit, then the DQ5 bit will be set (Exceeded Time Limit flag). This resetting of the counters is necessary since the Erase Suspend command can potentially interrupt or disrupt the high voltage pulses. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Write Operation Status
Table 8 Status Auto-Programming Program/Erase in Auto Erase In Progress Erase Suspended Read Mode (Sector being suspended erasure) Erase Suspended Read Mode (Sector not being suspended erasure) Exceeded Time Limits Auto-Programming Program/Erase in Auto-Erase Hardware Sequence Flags DQ7 DQ7 0 1 Data DQ7 0 DQ6 Toggle Toggle 1 Data Toggle Toggle DQ5 0 0 0 Data 1 1 DQ3 0 1 0 Data 0 1 (D) (Note 1) DQ2 to DQ0
Notes: 1. DQ0, DQ1, and DQ2 are reserve pins for future use. 2. DQ8 to DQ15 = DON'T CARE for x16 mode. 3. DQ4 is for Fujitsu internal use only.
17
MBM29F400TA/MBM29F400BA
DQ7 Data Polling The MBM29F400TA/BA device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 17. For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29F400TA/BA data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See Table 8.) See Figure 8 for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit The MBM29F400TA/BA also features the "Toggle Bit" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 9 for the Toggle Bit timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 2 and 3. 18
MBM29F400TA/MBM29F400BA
If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused. (Other sectors are still functional and can be reused.) The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the device was incorrectly used. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 8: Hardware Sequence Flags. RY/BY Ready/Busy The MBM29F400TA/BA provides a RY/BY output pin as a way to indicate to the host system that the EmbeddedTM Algorithms are either in progress or completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If the MBM29F400TA/ BA is placed in an Erase Suspend mode, the RY/BY output will be high. Also, since this is an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to VCC. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse in the four write pulse sequence. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse in the six write pulse sequence. The RY/BY pin should be ignored while RESET pin is at VIL. Refer to Figure 10, 11 for a detailed timing diagram.
19
MBM29F400TA/MBM29F400BA
RESET Hardware Reset The MBM29F400TA/BA device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset 20 s after the RESET pin is driven low. (Furthermore, once the RESET pin goes high, the device requires an additional 50 ns before it will allow read access.) When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 11 for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TA/BA device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tristated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to Figures 12 and 13 for the timing diagram.
Data Protection
The MBM29F400TA/BA is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
20
MBM29F400TA/MBM29F400BA
s ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. -45C to +125C Ambient Temperature with Power Applied................................................................... -25C to +85C Voltage with Respect to Ground All pins except A9, OE, and RESET (Note 1)........... -2.0 V to +7.0 V VCC (Note 1) ................................................................................................................ -2.0 V to +7.0 V A9, OE, and RESET (Note 2) ...................................................................................... -2.0 V to +13.5 V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During voltage transitions, outputs may overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE, and RESET pins are -0.5 V. During voltage transitions, A9, OE, and RESET may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET pins are +13.0 V which may overshoot to 13.5 V for periods of up to 20 ns. WARNING: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
s OPERATING RANGES
Commercial Devices Ambient Temperature (TA) ..................................0C to +70C VCC Supply Voltages VCC for MBM29F400TA-70/BA-70.......................+4.75 V to +5.25 V VCC for MBM29F400TA-90, 12 /BA-90, 12..........+4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed.
21
MBM29F400TA/MBM29F400BA
s MAXIMUM OVERSHOOT
+0.8 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Figure 1
Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V VCC + 0.5 V + 2.0 V
20 ns 20 ns
Figure 2
Maximum Positive Overshoot Waveform
20 ns
13.5 V +13.0 V VCC + 0.5 V
20 ns 20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3
Maximum Positive Overshoot Waveform
22
MBM29F400TA/MBM29F400BA
s DC CHARACTERISTICS
* TTL/NMOS Compatible Parameter Symbol ILI ILO ILIT ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH VLKO Parameter Description Input Leakage Current Output Leakage Current Input Leakage Current VCC Active Current (Note 1) VCC Active Current (Note 2) VCC Current (Standby) VCC Current (Standby, Reset) Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE, RESET) Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage VCC = 5.0 V IOL = 5.8 mA, VCC = VCC Min. IOH = -2.5 mA, VCC = VCC Min. -- Test Condition VIN = VSS to VCC, VCC = VCC Max. VOUT = VSS to VCC, VCC = VCC Max. VCC = VCC Max., A9, OE, RESET = 12.0 V Byte CE = VIL, OE = VIH Word CE = VIL, OE = VIH VCC = VCC Max., CE = VIH, RESET = VIH VCC = VCC Max., RESET = VIL -- -- -- -- -- -0.5 2.0 11.5 -- 2.4 3.2 -- 50 60 1.0 1.0 0.8 VCC+0.5 12.5 0.45 -- 4.2 mA mA mA V V V V V V Min. -- -- -- Max. 1.0 1.0 50 40 mA Unit A A A
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress.
23
MBM29F400TA/MBM29F400BA
* CMOS Compatible Parameter Symbol ILI ILO ILIT ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH1 Output High Voltage Level VOH2 VLKO Low VCC Lock-Out Voltage Parameter Description Input Leakage Current Output Leakage Current Input Leakage Current VCC Active Current (Note 1) VCC Active Current (Note 2) VCC Current (Standby) VCC Current (Standby, Reset) Input Low Level Input High Level Voltage for Autoselect and Sector Protect Output Low Voltage Level VCC = 5.0 V IOL = 5.8 mA, VCC = VCC Min. IOH = -2.5 mA, VCC = VCC Min. IOH = -100 A, VCC = VCC Min. -- Test Condition VIN = VSS to VCC, VCC = VCC Max. VCC = VCC Max., A9, OE, RESET = 12.0 V VOUT = VSS to VCC, VCC = VCC Max. Byte CE = VIL, OE = VIH Word CE = VIL, OE = VIH VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max., RESET = VCC 0.3 V -- -- -- -- -- -0.5 0.7 x VCC 11.5 -- 0.85 x VCC VCC - 0.4 3.2 -- 50 60 100 100 0.8 VCC + 0.3 12.5 0.45 -- -- 4.2 mA A A V V V V V V V Min. -- -- -- Max. 1.0 1.0 50 40 mA Unit A A A
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress.
24
MBM29F400TA/MBM29F400BA
s AC CHARACTERISTICS
* Read Only Operations Characteristics Parameter Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE or BYTE Switching Low or High -- Min. 70 70 70 30 20 20 0 20 5 90 90 90 35 20 20 0 20 5 120 120 120 50 30 30 0 20 5 ns ns ns ns ns ns ns s ns -70 -90 -12 (Note 1) (Note 2) (Note 2) Unit
Description
Test Setup
CE = VIL Max. OE = VIL OE = VIL Max. -- -- -- -- -- -- Max. Max. Max. Min. Max. Max.
Notes:1. Test Conditions: Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 2. Test Conditions: Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level .Input: 0.8 V and 2.0 V Output: 0.8 V and 2.0 V
25
MBM29F400TA/MBM29F400BA
5.0 V IN3064 or Equivalent Device Under Test 6.2 k CL Diodes = IN3064 or Equivalent
2.7 k
Notes: For -70: CL = 30 pF including jig capacitance For all others: CL = 100 pF including jig capacitance
Figure 4
Test Conditions
* Write/Erase/Program Operations Alternate WE Controlled Writes Parameter Symbol Description JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX -- -- Standard tWC tAS tAH tDS tDH tOES tOEH Write Cycle Time (Note 3) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note 3) Output Enable Hold Time Read (Note 3) Min. Min. Min. Min. Min. Min. Min. 70 0 45 30 0 0 0 10 90 0 45 45 0 0 0 10 120 0 50 50 0 0 0 10 ns ns ns ns ns ns ns ns -70 -90 -12 Unit
Toggle and Data Polling (Note 3) Min.
(Continued)
Notes: 1. 2. 3. 4. 26 This does not include the preprogramming time. These timings are for Sector Protection operation. Not 100% tested. Output Driver Disable Time.
MBM29F400TA/MBM29F400BA
(Continued)
Parameter Symbol Description JEDEC tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- Notes: 1. 2. 3. 4. Standard tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tVLHT tWPP tOESP tCSP tRP tFLQZ tBUSY Read Recover Time Before Write CE Setup Time CE Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Erase Operation (Note 1) Max. VCC Setup Time (Note 3) Voltage Transition Time (Notes 2, 3) Write Pulse Width (Note 2) OE Setup Time to WE Active (Notes 2, 3) CE Setup Time to WE Active (Note 3) RESET Pulse Width Min. Min. Min. Min. Min. Min. 30 50 4 100 4 4 500 20 30 30 50 4 100 4 4 500 30 35 30 50 4 100 4 4 500 30 50 sec s s s s s ns ns ns Min. Min. Min. Min. Min. Typ. Typ. 0 0 0 35 20 16 1.5 0 0 0 45 20 16 1.5 0 0 0 50 20 16 1.5 ns ns ns ns ns s sec -70 -90 -12 Unit
BYTE Switching Low to Output High-Z (Notes 3, 4) Max. Program/Erase Valid to RY/BY Delay (Note 3) Min.
This does not include the preprogramming time. These timings are for Sector Protection operation. Not 100% tested. Output Driver Disable Time.
27
MBM29F400TA/MBM29F400BA
* Write/Erase/Program Operations Alternate CE Controlled Writes Parameter Symbol Description JEDEC tAVAV tAVEL tELAX tDVEH tEHDX -- -- tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 -- -- -- -- Standard tWC tAS tAH tDS tDH tOES tOEH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 tVCS tRP tFLQZ tBUSY Write Cycle Time (Note 2) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Read (Note 2) Hold Time Toggle and Data Polling (Note 2) Read Recover Time Before Write WE Setup Time WE Hold Time CE Pulse Width CE Pulse Width High Byte Programming Operation Erase Operation (Note 1) Max. VCC Setup Time (Note 2) RESET Pulse Width Typ. Min. 30 50 500 20 30 30 50 500 30 35 30 50 500 30 50 sec s ns ns ns Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. 70 0 45 30 0 0 0 10 0 0 0 35 20 16 1.5 90 0 45 45 0 0 0 10 0 0 0 45 20 16 1.5 120 0 50 50 0 0 0 10 0 0 0 50 20 16 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns s sec -70 -90 -12 Unit
BYTE Switching Low to Output High-Z (Note 2) Max. Program/Erase Valid to RY/BY Delay (Note 2) Min.
Notes: 1. This does not include the preprogramming time. 2. Not 100% tested.
28
MBM29F400TA/MBM29F400BA
s SWITCHING WAVEFORMS
* Key to Switching Waveforms
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H DON'T CARE: Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
tRC
Addresses
Addresses Stable
tACC
CE
tOE (tDF)
OE
tOEH
WE
(tCE) (tOH)
Outputs
High-Z
Output Valid
High-Z
Figure 5
AC Waveforms for Read Operations
29
MBM29F400TA/MBM29F400BA
3rd Bus Cycle Addresses
5555H tWC tAS PA tAH
Data Polling
PA tRC
CE
tGHWL
OE
tWP
tWHWH1
WE
tCS tWPH tDF tOE PD DQ 7 DOUT tOH
tDH A0H
Data
tDS
5.0 V
tCE
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode.
Figure 6
Alternate WE Controlled Program Operation Timings
30
MBM29F400TA/MBM29F400BA
3rd Bus Cycle
Data Polling PA tAH tAS t WH PA
Addresses
5555H tWC
WE
tGHEL
OE
tCP
tWHWH1
CE
tWS tCPH
tDH
Data
A0H tDS
PD
DQ 7
DOUT
5.0 V
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode.
Figure 7
Alternate CE Controlled Program Operation Timings
31
MBM29F400TA/MBM29F400BA
tAH
Addresses
5555H tAS
2AAAH
5555H
5555H
2AAAH
SA
CE
tGHWL
OE
tWP
WE
tCS tWPH tDH
Data
AAH
55H
80H
AAH
55H
10H/ 30H
tDS
VCC
tVCS
Notes: 1. SA is the sector address for Sector Erase. Addresses = 5555H for Word, AAAAH for Byte. 2. These waveforms are for the x16 mode.
Figure 8
AC Waveforms Chip/Sector Erase Operations
32
MBM29F400TA/MBM29F400BA
CE
tCH tDF tOE
OE
tOEH
WE
tCE
*
DQ7 DQ7
tOH DQ7 = Valid Data High-Z
tWHWH1 or 2 DQ0 to DQ6 DQ0 to DQ6 Valid Data
DQ0 to DQ6 = Invalid
tOE * : DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 9
AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ6
Data (DQ0 to DQ7)
DQ6 = Toggle
DQ6 = Toggle
tOE
DQ6 = Stop Toggling
DQ0 to DQ7 Valid
* : DQ6 stops toggling. (The device has completed the Embedded operation.)
Figure 10
AC Waveforms for Toggle Bit during Embedded Algorithm Operations
33
MBM29F400TA/MBM29F400BA
CE
The rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
t BUSY
Figure 11
RY/BY Timing Diagram during Program/Erase Operations
CE
RY/BY
RESET
tRP tREADY
Figure 12
RESET/RY/BY Timing Diagram
34
MBM29F400TA/MBM29F400BA
CE
OE
BYTE
tELFL tELFH
DQ0 to DQ14
Data Output (DQ0 to DQ14) DQ15 Output
tFLQZ
Data Output (DQ0 to DQ7) Address Input
DQ15/A-1
Figure 13
BYTE Timing Diagram for Read Operations
CE
The falling edge of the last WE signal
WE
BYTE
tSET (tAS) tHOLD (tAH)
Figure 14
BYTE Timing Diagram for Write Operations
35
MBM29F400TA/MBM29F400BA
A17, A16 A15, A14 A13, A12 A0
SAX
SAY
A1
A6 12 V 5V A9
tVLHT
12 V 5V OE
tVLHT tWPP tVLHT
WE
tOESP
CE
tCSP
Data
tOE SAX: Sector Address for initial sector SAY: Sector Address for next sector Note: Byte mode: A-1 = VIL
01H
Figure 15
AC Waveforms for Sector Protection
RESET
12 V 5V
5V
CE
WE
tVLHT
Program or Erase Command Sequence
RY/BY
Figure 16 36
Temporary Sector Group Unprotection
MBM29F400TA/MBM29F400BA
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See Below)
Data Polling Device
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Figure 17
Embedded Programming Algorithm
Table 9 Bus Operation Standby* Write Read Standby*
Embedded Programming Algorithm Comment -- Valid Address/Data Sequence Data Polling to Verify Programming Compare Data Output to Data Expected
Command Sequence -- Program -- --
* : Device is either powered-down, erase inhibit or program inhibit. 37
MBM29F400TA/MBM29F400BA
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See Below) Data Polling or Toggle Bit Successfully Completed
Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH
Chip Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional sector erase commands are optional.
Sector Address/30H
Figure 18
Embedded Erase Algorithm
Table 10 Bus Operation Standby* Write Read Standby*
Embedded Erase Algorithm Comment -- -- Data Polling to Verify Erasure Compare Output to FFH
Command Sequence -- Erase -- --
* : Device is either powered-down, erase inhibit or program inhibit. 38
MBM29F400TA/MBM29F400BA
Start VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation. = XXXXH during chip erase
Read Byte (DQ0 to DQ7) Addr. = VA
DQ7 = Data ? No No DQ5 = 1 ? Yes Read Byte (DQ0 to DQ7) Addr. = VA
Yes
DQ7 = Data ? No Fail
Yes
Pass
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 19
Data Polling Algorithm
39
MBM29F400TA/MBM29F400BA
Start
Read Byte (DQ0 to DQ7) Addr. = H or L
DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0 to DQ7) Addr. = VA
No
DQ6 = Toggle ? Yes Fail
No
Pass
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1" .
Figure 20
Toggle Bit Algorithm
40
MBM29F400TA/MBM29F400BA
Start
Set Up Sector Addr. (A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID, A6 = CE = VIL, RESET = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 s
WE = VIH, CE = OE = VIL A9 should remain VID
Read from Sector Addr. = SA, A0 = 0, A1 = 1, A6 = 0 No No PLSCNT = 25 ? Yes Remove VID from A9 Write Reset Command Data = 01H ? Yes Yes Protect Another Sector? No Device Failed Remove VID from A9 Write Reset Command
Sector Protection Completed
Figure 21
Sector Protection Algorithm
41
MBM29F400TA/MBM29F400BA
Start
RESET = VID (Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Unprotection Completed (Note 2)
Notes:1. All protected sectors are unprotected. 2. All previously protected sectors are protected once again.
Figure 22
Temporary Sector Unprotection Algorithm
42
MBM29F400TA/MBM29F400BA
s ERASE AND PROGRAMMING PERFORMANCE
Limit Parameter Min. Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ. 1.5 16 8.5 1,000,000 Max. 30 1,000 50 -- sec s sec Cycles Excludes 00H programming prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comment
s TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. 8 8 8.5 Max. 9 10 11.5 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz
s SOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. 7.5 8 8.5 Max. 9 10 11 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz
43
MBM29F400TA/MBM29F400BA
s PACKAGE DIMENSIONS
(Suffix: PFN)
44 pin, Plastic SOP (FPT-44P-M16)
28.45 -0.20 1.120 -.008
+0.25 +.010
*1 Resin Protrusion:(Each Side:0.15(.006)MAX) *2 Resin Protrusion:(Each Side:0.38(.015)MAX)
2.50(.098)MAX
(MOUNTING HEIGHT)
44
23
0.800.20 (.031.008)
13.000.10 (.512.004)
16.000.20 (.630.008)
14.400.20 (.567.008)
INDEX "A"
LEAD No.
1
1.27(.050)NOM
22
0.150.05 (.006.002)
0.10(.004)
0.40 -0.05 +.004 .016 -.002 26.67(1.050)REF
+0.10
O0.13(.005)
M
0(0)MIN (STAND OFF)
Dimensions in mm(inches)
C
1995 FUJITSU LIMITED F44023S-2C-1
44
MBM29F400TA/MBM29F400BA
(Suffix: PFTN)
48 pin, Plastic TOSP(I)
(FPT-48P-M19)
LEAD No.
1 48
INDEX
Details of "A" part 0.15(.006) MAX
"A" 0.15(.006)
0.35(.014) MAX 0.25(.010)
24
25
20.000.20 (.787.008) * 18.400.20 (.724.008)
* 12.000.20 (.472.008) 11.50REF (.460)
1.10 -0.05 +.004 .043 -.002
+0.10
(mounting height)
0.10(.004)
0.50(.0197) TYP 0.150.05 (.006.002) 0.200.10 (.008.004)
0.05(0.02)MIN STAND OFF 0.10(.004)
M
19.000.20 (.748.008)
0.500.10 (.020.004)
Dimensions in mm(inches).
C
1996 FUJITSU LIMITED F48029S-1C-2
45
MBM29F400TA/MBM29F400BA
(Suffix: PFTR)
48 pin, Plastic TOSP(I)
(FPT-48P-M20)
LEAD No.
1 48
INDEX
Details of "A" part 0.15(.006) MAX
"A" 0.15(.006)
0.35(.014) MAX 0.25(.010)
24
25
19.000.20 (.748.008)
0.500.10 (.020.004) 0.150.10 (.006.002) 0.200.10 (.008.004) 0.10(.004)
M
0.10(.004)
0.50(.0197) TYP
0.05(0.02)MIN STAND OFF
* 18.400.20 (.724.008) 20.000.20 (.787.008)
11.50(.460)REF * 12.000.20(.472.008)
1.10 -0.05 +.004 .043 -.002
+0.10
(mounting height)
Dimensions in mm(inches).
C
1996 FUJITSU LIMITED F48030S-1C-2
46
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

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